There are many integrated circuit (IC) chip, or die, packaging technologies. A number of advanced IC packages include a plurality of IC chips in a stack, which reduce the footprint of the IC chips to improve packaged device density within a given platform (e.g., mobile device, computer, automobile). For stacked memory chips, a first memory IC chip may be stacked over a second memory IC chip 110, the second memory IC chip may be further stacked over a third IC chip, and so on. Between each IC chip there is typically a die attach material (e.g., paste or film). To accommodate electrical connection (e.g., power, signal, ground) by wire bonds, stacked chips may be laterally offset or displaced in one or more dimensions relative to an underlying/overlying chip. The wire bonds may be waterfalled from a top most chip to successively lower chips until landing on a package substrate or on a bottom die that is coupled to a substrate through bumps. Waterfalled wire bonds are typical in applications where the chips in the stack are the same and various pads on each chip may be powered, grounded, or signaled concurrently with corresponding pads on another chip. This wire bond architecture is common for a NAND flash memory chip stack, which often accommodates metal features on one or two sides of the chip. Wire bonding an IC chip stack typically requires a footprint that is a function of both the chip size and the cumulative chip offset required for the wire bonds. As such, wire bonding the chip stack typically increases package size well beyond that of a single IC chip.
In alternative architectures, through-substrate vias (TSVs) may be fabricated into one or more of the IC chips in a stack. No offsets between stacked chips are needed in a TSV-based architecture, however TSVs are expensive to manufacture, reduce the device and/or trace routing density, and can detrimentally impact the performance of the active devices in a chip.
In still other 3D stacked-chip architectures, a smaller chip is bumped face-to-face with a larger chip and then pads on the larger chip's face not covered by the smaller chip are further bonded to a package substrate. Such an architecture often limits the minimum footprint of the larger die and/or package substrate.